View EBE21RD4AGFA-6E-E_1235673.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DATA SHEET
2GB Registered DDR2 SDRAM DIMM
EBE21RD4AGFA (256M words x 72 bits, 2 Ranks)
Description
The EBE21RD4AGFA is a 256M words x 72 bits, 2 ranks DDR2 SDRAM Module, mounting 36 pieces of 512M bits DDR2 SDRAM sealed in FBGA (BGA) package. Read and write operations are performed at the cross points of the CK and the /CK. This highspeed data transfer is realized by the 4bits prefetchpipelined architecture. Data strobe (DQS and /DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each FBGA (BGA) on the module board. Note: Do not push the cover or drop the modules in order to avoid mechanical defects, which may result in electrical defects.
Features
* 240-pin socket type dual in line memory module (DIMM) PCB height: 30.0mm Lead pitch: 1.0mm Lead-free (RoHS compliant) * Power supply: VDD = 1.8V 0.1V * Data rate: 667Mbps/533Mbps/400Mbps (max.) * SSTL_18 compatible I/O * Double-data-rate architecture: two data transfers per clock cycle * Bi-directional, data strobe (DQS and /DQS) is transmitted /received with data, to be used in capturing data at the receiver * DQS is edge aligned with data for READs; center aligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive CK edge; data referenced to both edges of DQS * Four internal banks for concurrent operation (components) * Burst length: 4, 8 * /CAS latency (CL): 3, 4, 5 * Auto precharge option for each burst access * Auto refresh and self refresh modes * Average refresh period 7.8s at 0C TC +85C 3.9s at +85C < TC +95C * Posted CAS by programmable additive latency for better command and data bus efficiency * Off-Chip-Driver Impedance Adjustment and On-DieTermination for better signal quality * /DQS can be disabled for single-ended Data Strobe operation * 1 piece of PLL clock driver, 4 piece of register driver and 1 piece of serial EEPROM (2k bits EEPROM) for Presence Detect (PD)
Document No. E0794E20 (Ver. 2.0) Date Published October 2005 (K) Japan Printed in Japan URL: http://www.elpida.com Elpida Memory, Inc. 2005
EBE21RD4AGFA
Ordering Information
Data rate Mbps (max.) 667 Component 1 JEDEC speed bin* (CL-tRCD-tRP) DDR2-667 (5-5-5) DDR2-533 (4-4-4) DDR2-400 (3-3-3) 240-pin DIMM (lead-free) Gold Contact pad
Part number EBE21RD4AGFA-6E-E
Package
Mounted devices EDE5104AGSE-6E-E EDE5104AGSE-6E-E EDE5104AGSE-5C-E EDE5104AGSE-6E-E EDE5104AGSE-5C-E EDE5104AGSE-4A-E
EBE21RD4AGFA-5C-E 533 EBE21RD4AGFA-4A-E 400
Note: 1. Module /CAS latency = component CL + 1.
Pin Configurations
Front side 1 pin 64 pin 65 pin 120 pin
121 pin Back side
184 pin 185 pin
240 pin
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Pin name VREF VSS DQ0 DQ1 VSS /DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS /DQS1 DQS1 VSS /RESET NC VSS DQ10 DQ11 VSS DQ16 DQ17
Pin No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85
Pin name A4 VDD A2 VDD VSS VSS VDD NC/Par_In VDD A10 BA0 VDD /WE /CAS VDD /CS1 ODT1 VDD VSS DQ32 DQ33 VSS /DQS4 DQS4 VSS
Pin No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145
Pin name VSS DQ4 DQ5 VSS DQS9 /DQS9 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DQS10 /DQS10 VSS NC NC VSS DQ14 DQ15 VSS DQ20 DQ21 VSS
Pin No. 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205
Pin name VDD A3 A1 VDD CK0 /CK0 VDD A0 VDD BA1 VDD /RAS /CS0 VDD ODT0 A13 VDD VSS DQ36 DQ37 VSS DQS13 /DQS13 VSS DQ38
Data Sheet E0794E20 (Ver. 2.0)
2
EBE21RD4AGFA
Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Pin name VSS /DQS2 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS /DQS3 DQS3 VSS DQ26 DQ27 VSS CB0 CB1 VSS /DQS8 DQS8 VSS CB2 CB3 VSS VDD CKE0 VDD NC NC/Err_Out VDD A11 A7 VDD A5 Pin No. 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Pin name DQ34 DQ35 VSS DQ40 DQ41 VSS /DQS5 DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS SA2 NC VSS /DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS /DQS7 DQS7 VSS DQ58 DQ59 VSS SDA SCL Pin No. 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 Pin name DQS11 /DQS11 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS12 /DQS12 VSS DQ30 DQ31 VSS CB4 CB5 VSS DQS17 /DQS17 VSS CB6 CB7 VSS VDD CKE1 VDD NC NC VDD A12 A9 VDD A8 A6 Pin No. 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Pin name DQ39 VSS DQ44 DQ45 VSS DQS14 /DQS14 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS NC NC VSS DQS15 /DQS15 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS16 /DQS16 VSS DQ62 DQ63 VSS VDDSPD SA0 SA1
Data Sheet E0794E20 (Ver. 2.0)
3
EBE21RD4AGFA
Pin Description
Pin name A0 to A13 A10 (AP) BA0, BA1 DQ0 to DQ63 CB0 to CB7 /RAS /CAS /WE /CS0, /CS1 CKE0, CKE1 CK0 /CK0 DQS0 to DQS17, /DQS0 to /DQS17 SCL SDA SA0 to SA2 VDD VDDSPD VREF VSS ODT0, ODT1 /RESET Par_In*
2 2
Function Address input Row address Column address Auto precharge Bank select address Data input/output Check bit (Data input/output) Row address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input and output data strobe Clock input for serial PD Data input/output for serial PD Serial address input Power for internal circuit Power for serial EEPROM Input reference voltage Ground ODT control Reset pin (forces register and PLL inputs low) * Parity bit for the address and control bus Parity error found on the address and control bus No connection
1
A0 to A13 A0 to A9, A11
Err_Out* NC
Notes: 1. Reset pin is connected to both OE of PLL and reset to register. 2. NC/Err_Out (Pin No. 55) and NC/Par_In (Pin No. 68) are for optional function to check address and command parity.
Data Sheet E0794E20 (Ver. 2.0)
4
EBE21RD4AGFA
Serial PD Matrix*1
Byte No. Function described 0 1 2 3 4 5 6 7 8 9 Number of bytes utilized by module manufacturer Total number of bytes in serial PD device Memory type Number of row address Number of column address Number of DIMM ranks Module data width Module data width continuation Bit7 1 0 0 0 0 0 0 0 Bit6 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 Bit5 0 0 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 1 Bit4 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 0 1 Bit3 0 1 1 1 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 1 Bit2 0 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 1 1 0 1 1 0 0 0 0 0 1 0 0 0 0 0 1 Bit1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Bit0 0 0 0 0 1 1 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 0 0 0 0 Hex value 80H 08H 08H 0EH 0BH 61H 48H 00H 05H 30H 3DH 50H 45H 50H 60H 02H 82H 04H 04H 00H 0CH 04H 38H 01H 01H 00H 03H 3DH 50H 50H 60H 50H 60H 3CH Comments 128 bytes 256 bytes DDR2 SDRAM 14 11 2 72 0 SSTL 1.8V 3.0ns*
1
Voltage interface level of this assembly 0 DDR SDRAM cycle time, CL = 5 -6E -5C -4A 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3.75ns* 5.0ns*
1
1
10
SDRAM access from clock (tAC) -6E -5C -4A
0.45ns* 0.5ns* 0.6ns* ECC 7.8s x4 x4 0 4,8 4 3, 4, 5
1 1
1
11 12 13 14 15 16 17 18 19 20 21 22 23
DIMM configuration type Refresh rate/type Primary SDRAM width Error checking SDRAM width Reserved SDRAM device attributes: Burst length supported SDRAM device attributes: Number of banks on SDRAM device SDRAM device attributes: /CAS latency DIMM Mechanical Characteristics DIMM type information SDRAM module attributes SDRAM device attributes: General Minimum clock cycle time at CL = 4 -6E, -5C -4A Maximum data access time (tAC) from clock at CL = 4 -6E, -5C -4A
4.00mm max. Registered Normal Weak Driver 50 ODT Support 3.75ns* 5.0ns* 0.5ns* 0.6ns* 5.0ns* 0.6ns* 15ns
1 1
24
1
1 1
25 26 27
Minimum clock cycle time at CL = 3 Maximum data access time (tAC) from clock at CL = 3 Minimum row precharge time (tRP)
1
Data Sheet E0794E20 (Ver. 2.0)
5
EBE21RD4AGFA
Byte No. 28 29 30
Function described Minimum row active to row active delay (tRRD) Minimum active to precharge time (tRAS) -6E, -5C -4A
Bit7 0
Bit6 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
Bit5 0 1 1 1 0 1 1 1 1 1 0 0 0 0 1 1 1 0 1 0 0 0 1 1 1 0 0 0 1 1 1 1 0
Bit4 1 1 0 0 0 0 0 1 0 1 0 1 1 1 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 0
Bit3 1 1 1 1 0 0 0 0 1 1 1 0 0 1 0 1 1 1 1 1 0 0 1 0 1 0 1 1 0 0 1 1 1
Bit2 1 1 1 0 0 0 1 1 0 0 0 0 1 0 0 0 1 1 0 1 0 0 1 1 0 0 0 1 0 0 0 1 1
Bit1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 1 0 0 0 1 1 1 0 0 1
Bit0 0 0 1 0 1 0 1 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 1
Hex value 1EH 3CH 2DH 28H 01H 20H 25H 35H 28H 38H 48H 10H 15H 18H 23H 28H 3CH 1EH 28H 1EH 00H 00H 3CH 37H 69H 80H 18H 1EH 23H 22H 28H 2DH 0FH
Comments 7.5ns 15ns 45ns 40ns 1GB 0.20ns* 0.25ns* 0.35ns* 0.28ns* 0.38ns* 0.48ns* 0.10ns* 0.15ns* 0.18ns* 0.23ns* 0.28ns* 15ns*
1 1
Minimum /RAS to /CAS delay (tRCD) 0 0 0 0 0 0 0 0 0 0 0 0
31 32
Module rank density Address and command setup time before clock (tIS) -6E -5C -4A
1 1
33
Address and command hold time after clock (tIH) -6E -5C -4A
1
1 1
34
Data input setup time before clock (tDS) -6E, -5C -4A
1
1
35
Data input hold time after clock (tDH) 0 -6E -5C -4A 0 0 0
1
1 1
36 37
Write recovery time (tWR)
Internal write to read command delay (tWTR) 0 -6E, -5C -4A 0 Internal read to precharge command 0 delay (tRTP) Memory analysis probe 0 characteristics Extension of Byte 41 and 42 Active command period (tRC) -6E, -5C -4A Auto refresh to active/ Auto refresh command cycle (tRFC) SDRAM tCK cycle max. (tCK max.) Dout to DQS skew -6E -5C -4A 0 0 0 0 1 0 0 0 0 0 0 0
7.5ns* 10ns*
1
1
38 39 40 41
7.5ns* TBD
1
Undefined 60ns* 55ns*
1
1
42 43 44
105ns* 8ns*
1
1
0.24ns* 0.30ns* 0.35ns* 0.34ns* 0.40ns* 0.45ns* 15s
1
1 1
45
Data hold skew (tQHS) -6E -5C -4A
1
1 1
46
PLL relock time
Data Sheet E0794E20 (Ver. 2.0)
6
EBE21RD4AGFA
Byte No. 47 to 61 62 63
Function described
Bit7 0
Bit6 0 0 0 1 1 1 1 0 x 1 1 1 0 0 1 1 0 1 1 1 1 0 0 0 0 1 1 1 0 1 0 0 0 x x
Bit5 0 0 0 0 0 1 1 0 x 0 0 0 1 1 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 x x
Bit4 0 1 0 1 0 1 1 0 x 0 0 0 1 1 1 0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 x x
Bit3 0 0 1 0 1 1 1 0 x 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 x x
Bit2 0 0 1 0 1 1 1 0 x 1 0 1 0 0 0 1 1 0 1 1 0 1 1 1 1 1 0 0 1 1 0 0 0 x x
Bit1 0 1 1 1 0 1 1 0 x 0 1 0 1 0 1 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 0 0 0 x x
Bit0 0 0 0 0 0 1 0 0 x 1 0 1 0 1 0 0 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 x x
Hex value 00H 12H 0EH 52H CCH 7FH FEH 00H xx 45H 42H 45H 32H 31H 52H 44H 34H 41H 47H 46H 41H 2DH 36H 35H 34H 45H 43H 41H 2DH 45H 20H 30H 20H xx xx
Comments
SPD Revision Checksum for bytes 0 to 62 -6E -5C -4A
0 0 0 1 0 1 0 x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x
Rev. 1.2
64 to 65 66 67 to 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
Manufacturer's JEDEC ID code Manufacturer's JEDEC ID code Manufacturer's JEDEC ID code Manufacturing location Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number -6E -5C -4A
Continuation code Elpida Memory
(ASCII-8bit code) E B E 2 1 R D 4 A G F A -- 6 5 4 E C A -- E (Space) Initial (Space) Year code (BCD) Week code (BCD)
87
Module part number -6E -5C -4A
88 89 90 91 92 93 94 95 to 98 99 to 127
Module part number Module part number Module part number Revision code Revision code Manufacturing date Manufacturing date Module serial number Manufacture specific data
Notes: 1. These specifications are defined based on component specification, not module.
Data Sheet E0794E20 (Ver. 2.0)
7
EBE21RD4AGFA
Block Diagram
VSS /RCS1 /RCS0 DQS0 /DQS0
RS RS DM /CS 4 RS DQS /DQS DM /CS DQ0 to DQ3 DQS /DQS
DQS9 /DQS9 4 DQ4 to /DQ7
RS RS DM RS /CS DQS /DQS DM /CS DQS /DQS
DQ0 to DQ3 RS RS
DQ0 to DQ3
D0
D18
DQ0 to DQ3
D9
DQ0 to DQ3
D27
DQS1 /DQS1
DQS10 /DQS10 DM /CS DQS /DQS DM /CS DQ0 to DQ3 DQS /DQS RS
RS RS DM /CS DQS /DQS DM /CS DQS /DQS
DQ8 to DQ11
4
DQ0 to DQ3
D1
D19
DQ12 to DQ15
4
RS
DQ0 to DQ3
D10
DQ0 to DQ3
D28
DQS2 /DQS2
RS RS DM /CS DQS /DQS DM /CS DQ0 to DQ3 DQS /DQS
DQS11 /DQS11 RS
RS RS DM /CS DQS /DQS DM /CS DQS /DQS
DQ16 to DQ19
4
DQ0 to DQ3
D2
D20
DQ20 to DQ23
4
RS
DQ0 to DQ3
D11
DQ0 to DQ3
D29
DQS3 /DQS3
RS RS DM /CS DQS /DQS DM /CS DQ0 to DQ3 DQS /DQS
DQS12 /DQS12 RS
RS RS DM 4 /CS DQS /DQS DM DQ0 to DQ3 CS DQS /DQS
DQ24 to DQ27
4
DQ0 to DQ3
D3
D21
DQ28 to DQ31 RS RS
RS
DQ0 to DQ3
D12
D30
DQS4 /DQS4
RS RS DM /CS DQS /DQS DM /CS DQ0 to DQ3 DQS /DQS
DQS13 /DQS13 RS
DM DQ36 to DQ39 4 RS
/CS DQS /DQS
DM
/CS DQS /DQS
DQ32 to DQ35
4
DQ0 to DQ3
D4
D22
DQ0 to DQ3
D13
DQ0 to DQ3
D31
DQS5 /DQS5
RS RS DM /CS DQS /DQS DM /CS DQ0 to DQ3 DQS /DQS
DQS14 /DQS14 RS
RS RS DM /CS DQS /DQS DM DQ0 to DQ3 /CS DQS /DQS
DQ40 to DQ43
4
DQ0 to DQ3
D5
D23
DQ44 to DQ47
4
RS
DQ0 to DQ3
D14
D32
RS DQS6 /DQS6 RS DM /CS DQ48 to DQ51 4 RS DQ0 to DQ3 DQS /DQS DM /CS DQ0 to DQ3 DQS /DQS
DQS15 /DQS15
RS RS DM /CS DQS /DQS DM /CS DQS /DQS
D6
D24
DQ52 to DQ55
4
RS
DQ0 to DQ3
D15
DQ0 to DQ3
D33
DQS7 /DQS7
RS RS DM /CS DQS /DQS DM /CS DQ0 to DQ3 DQS /DQS
DQS16 /DQS16 RS
RS RS DM /CS DQS /DQS DM /CS DQS /DQS
DQ56 to DQ59
4
DQ0 to DQ3
D7
D25
DQ60 to DQ63
4
RS
DQ0 to DQ3
D16
DQ0 to DQ3
D34
DQS8 /DQS8
RS RS DM /CS DQS /DQS DM /CS DQ0 to DQ3 DQS /DQS
DQS17 /DQS17 RS
RS RS DM /CS DQS /DQS DM /CS DQS /DQS
CB0 to CB3
4
DQ0 to DQ3
D8
D26
CB4 to CB7
4
RS
DQ0 to DQ3
D17
DQ0 to DQ3
D35
/CS0*2 /CS1*2 BA0 to BA1 A0 to A13 /RAS /CAS CKE0 CKE1 /WE /ODT0 /ODT1
RS RS RS RS RS RS RS RS RS RS RS
/RCS0 -> /CS: SDRAMs D0 to D17 /RCS1 -> /CS: SDRAMs D18 to D35 R E G I S T E R RBA0 to RBA1 -> BA0 to BA1: SDRAMs D0 to D35 RA0 to RA13 -> A0 to A13: SDRAMs D0 to D35 /RRAS -> /RAS: SDRAMs D0 to D35 /RCAS -> /CAS: SDRAMs D0 to D35 RCKE0 -> CKE: SDRAMs D0 to D17 RCKE1 -> CKE: SDRAMs D18 to D35 /RWE -> /WE: SDRAMs D0 to D35 RODT0 -> ODT: SDRAMs D0 to D17 /RST RODT1 -> ODT: SDRAMs D18 to D35
Serial PD SCL SCL SDA SDA
U0
WP A0 A1 A2 SA0 SA1 SA2
D0 to D35: 512M bits DDR2 SDRAM U0: 2k bits EEPROM RS: 22 PLL: CUA877 Register: SSTUA32866
/RESET*3 PCK7*3
/PCK7*3 CK0 /CK0 /RESET P L L OE
Notes: 1. DQ wring may be changed within a nibble. 2. /CS0 connects to D/CS and /CS1 connects to /CSR on D0 to D35 VREF register1 and register2. VSS D0 to D35 /CS1 connects to D/CS and /CS0 connects to /CSR on register3 and register4. 3. /RESET, PCK7 and /PCK7 connect to all registers. PCK0 to PCK6, PCK8, PCK9 -> CK: SDRAMs D0 to D35 CKE and /ODT connect to a register. /PCK0 to /PCK6, /PCK8, /PCK9 -> /CK: SDRAMs D0 to D35 Other signals connect to two of four registers. PCK7 -> CK: register /PCK7 -> /CK: register VDD
VDDSPD
Serial PD D0 to D35
Data Sheet E0794E20 (Ver. 2.0)
8
EBE21RD4AGFA
Differential Clock Net Wiring (CK0, /CK0)
0ns (nominal) SDRAM
PLL OUT1
120
CK0
120 IN
SDRAM
/CK0
Register 1 C Register 3 120 C Feedback out C Register 4 120 OUT'N' Feedback in Register 2 120
Notes: 1. The clock delay from the input of the PLL clock to the input of any SDRAM or register willl be set to 0ns (nominal). 2. Input, output and feedback clock lines are terminated from line to line as shown, and not from line to ground. 3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired in a similar manner. 4. Termination resistors for the PLL feedback path clocks are located as close to the input pin of the PLL as possible.
Data Sheet E0794E20 (Ver. 2.0)
9
EBE21RD4AGFA
Electrical Specifications
* All voltages are referenced to VSS (GND). Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating case temperature Storage temperature Symbol VT VDD IOS PD TC Tstg Value -0.5 to +2.3 -0.5 to +2.3 50 18 0 to +95 -55 to +100 Unit V V mA W C C 1, 2 1 1 Note 1
Notes: 1 DDR2 SDRAM component specification. 2. Supporting 0C to +85C and being able to extend to +95C with doubling auto-refresh commands in frequency to a 32ms period (tREFI = 3.9s) and higher temperature self-refresh entry via the control of EMRS (2) bit A7 is required. Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. DC Operating Conditions (TC = 0C to +85C) (DDR2 SDRAM Component Specification)
Parameter Supply voltage Symbol VDD, VDDQ VSS VDDSPD Input reference voltage Termination voltage DC input logic high DC input low AC input logic high -6E -5C, -4A AC input low -6E -5C, -4A VREF VTT VIH (DC) VIL (DC) VIH (AC) VIH (AC) VIL (AC) VIL (AC) min. 1.7 0 1.7 0.49 x VDDQ VREF - 0.04 VREF + 0.125 -0.3 VREF + 0.200 VREF + 0.250 typ. 1.8 0 -- max. 1.9 0 3.6 Unit V V V V V V V V V V V 1, 2 3 Notes 4
0.50 x VDDQ 0.51 x VDDQ VREF VREF + 0.04 VDDQ + 0.3 VREF - 0.125 VREF - 0.200 VREF - 0.250
Notes: 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF are expected to track variations in VDDQ. 2. Peak to peak AC noise on VREF may not exceed 2% VREF (DC). 3. VTT of transmitting device must track VREF of receiving device. 4. VDDQ must be equal to VDD.
Data Sheet E0794E20 (Ver. 2.0)
10
EBE21RD4AGFA
DC Characteristics 1 (TC = 0C to +85C, VDD = 1.8V 0.1V, VSS = 0V)
Parameter Symbol Grade -6E -5C -4A max 3970 3660 3250 Unit Test condition one bank; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS min.(IDD); CKE is H, /CS is H between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING one bank; IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS min.(IDD); tRCD = tRCD (IDD); CKE is H, /CS is H between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W all banks idle; tCK = tCK (IDD); CKE is L; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING all banks idle; tCK = tCK (IDD); CKE is H, /CS is H; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING all banks idle; tCK = tCK (IDD); CKE is H, /CS is H; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING all banks open; tCK = tCK (IDD); Fast PDN Exit CKE is L; MRS(12) = 0 Other control and address bus inputs are STABLE; Slow PDN Exit Data bus inputs are MRS(12) = 1 FLOATING all banks open; tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD); CKE is H, /CS is H between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING all banks open, continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD); CKE is H, /CS is H between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W all banks open, continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD); CKE is H, /CS is H between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating current (ACT-PRE)
IDD0
mA
Operating current (ACT-READ-PRE)
IDD1
-6E -5C -4A
4320 3980 3560
mA
Precharge power-down standby current
IDD2P
-6E -5C -4A
970 930 810
mA
Precharge quiet standby current
IDD2Q
-6E -5C -4A
1510 1470 1250
mA
Idle standby current
IDD2N
-6E -5C -4A
1870 1650 1430
mA
Active power-down standby current
-6E IDD3P-F -5C -4A -6E IDD3P-S -5C -4A
2050 2010 1790 1510 1470 1250
mA
mA
Active standby current
IDD3N
-6E -5C -4A
3160 2940 2710
mA
Operating current (Burst read operating)
IDD4R
-6E -5C -4A
5620 4830 4140
mA
Operating current (Burst write operating)
IDD4W
-6E -5C -4A
5440 4830 4140
mA
Data Sheet E0794E20 (Ver. 2.0)
11
EBE21RD4AGFA
Parameter
Symbol
Grade -6E -5C -4A
max 6790 6200 5710
Unit
Test condition tCK = tCK (IDD); Refresh command at every tRFC (IDD) interval; CKE is H, /CS is H between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self Refresh Mode; CK and /CK at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING all bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD (IDD) -1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD), tRCD = 1 x tCK (IDD); CKE is H, CS is H between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4W;
Auto-refresh current
IDD5
mA
Self-refresh current
IDD6
310
mA
Operating current (Bank interleaving)
IDD7
-6E -5C -4A
7730 7420 6850
mA
Notes: 1. 2. 3. 4.
IDD specifications are tested after the device is properly initialized. Input slew rate is specified by AC Input Test Condition. IDD parameters are specified with ODT disabled. Data bus consists of DQ, DM, DQS, /DQS, RDQS, /RDQS, LDQS, /LDQS, UDQS, and /UDQS. IDD values must be met with all combinations of EMRS bits 10 and 11. 5. Definitions for IDD L is defined as VIN VIL (AC) (max.) H is defined as VIN VIH (AC) (min.) STABLE is defined as inputs stable at an H or L level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: inputs changing between H and L every other clock cycle (once per two clocks) for address and control signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals not including masks or strobes. 6. Refer to AC Timing for IDD Test Conditions.
AC Timing for IDD Test Conditions For purposes of IDD testing, the following parameters are to be utilized.
DDR2-667 Parameter CL(IDD) tRCD(IDD) tRC(IDD) tRRD(IDD) tCK(IDD) tRAS(min.)(IDD) tRAS(max.)(IDD) tRP(IDD) tRFC(IDD) 5-5-5 5 15 60 7.5 3 45 70000 15 105 DDR2-533 4-4-4 4 15 60 7.5 3.75 45 70000 15 105 DDR2-400 3-3-3 3 15 55 7.5 5 40 70000 15 105 Unit tCK ns ns ns ns ns ns ns ns
Data Sheet E0794E20 (Ver. 2.0)
12
EBE21RD4AGFA
DC Characteristics 2 (TC = 0C to +85C, VDD, VDDQ = 1.8V 0.1V) (DDR2 SDRAM Component Specification)
Parameter Input leakage current Output leakage current Symbol ILI ILO Value 2 5 VTT + 0.603 VTT - 0.603 0.5 x VDDQ +13.4 -13.4 Unit A A V V V mA mA Notes VDD VIN VSS VDDQ VOUT VSS 5 5 1 3, 4, 5 2, 4, 5
Minimum required output pull-up under AC VOH test load Maximum required output pull-down under VOL AC test load Output timing measurement reference level VOTR Output minimum sink DC current Output minimum source DC current IOL IOH
Notes: 1. 2. 3. 4. 5.
The VDDQ of the device under test is referenced. VDDQ = 1.7V; VOUT = 1.42V. VDDQ = 1.7V; VOUT = 0.28V. The DC value of VREF applied to the receiving device is expected to be set to VTT. After OCD calibration to 18 at TC = 25C, VDD = VDDQ = 1.8V.
DC Characteristics 3 (TC = 0C to +85C, VDD, VDDQ = 1.8V 0.1V) (DDR2 SDRAM Component Specification)
Parameter AC differential input voltage AC differential cross point voltage AC differential cross point voltage Symbol VID (AC) VIX (AC) VOX (AC) min. 0.5 0.5 x VDDQ - 0.175 0.5 x VDDQ - 0.125 max. VDDQ + 0.6 0.5 x VDDQ + 0.175 0.5 x VDDQ + 0.125 Unit V V V Note 1, 2 2 3
Notes: 1. VID(AC) specifies the input differential voltage |VTR -VCP| required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as /CK, /DQS, /LDQS or /UDQS). The minimum value is equal to VIH(AC) - VIL(AC). 2. The typical value of VIX(AC) is expected to be about 0.5 x VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ . VIX(AC) indicates the voltage at which differential input signals must cross. 3. The typical value of VOX(AC) is expected to be about 0.5 x VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ . VOX(AC) indicates the voltage at which differential output signals must cross.
VDDQ VTR
VID
VCP VSSQ
Crossing point
VIX or VOX
Differential Signal Levels*1, 2
Data Sheet E0794E20 (Ver. 2.0)
13
EBE21RD4AGFA
ODT DC Electrical Characteristics (TC = 0C to +85C, VDD, VDDQ = 1.8V 0.1V) (DDR2 SDRAM Component Specification)
Parameter Rtt effective impedance value for EMRS (A6, A2) = 0, 1; 75 Rtt effective impedance value for EMRS (A6, A2) = 1, 0; 150 Rtt effective impedance value for EMRS (A6, A2) = 1, 1; 50 Deviation of VM with respect to VDDQ/2 Symbol Rtt1(eff) Rtt2(eff) Rtt3(eff) VM min 60 120 40 -6 typ 75 150 50 max 90 180 60 +6 Unit % Notes 1 1 1 1
Note: 1. Test condition for Rtt measurements. Measurement Definition for Rtt(eff) Apply VIH (AC) and VIL (AC) to test pin separately, then measure current I(VIH(AC)) and I(VIL(AC)) respectively. VIH(AC), and VDDQ values defined in SSTL_18.
Rtt(eff) =
VIH(AC) - VIL(AC) I(VIH(AC)) - I(VIL(AC))
Measurement Definition for VM Measure voltage (VM) at test pin (midpoint) with no load.
VM =
2 x VM VDDQ
- 1 x 100%
OCD Default Characteristics (TC = 0C to +85C, VDD, VDDQ = 1.8V 0.1V) (DDR2 SDRAM Component Specification)
Parameter Output impedance Pull-up and pull-down mismatch Output slew rate min 12.6 0 1.5 typ 18 max 23.4 4 5 Unit V/ns Notes 1 1, 2 3, 4
Notes: 1. Impedance measurement condition for output source DC current: VDDQ = 1.7V; VOUT = 1420mV; (VOUT-VDDQ)/IOH must be less than 23.4 for values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement condition for output sink DC current: VDDQ = 1.7V; VOUT = 280mV; VOUT/IOL must be less than 23.4 for values of VOUT between 0V and 280mV. 2. Mismatch is absolute value between pull up and pull down, both are measured at same temperature and voltage. 3. Slew rate measured from VIL(AC) to VIH(AC). 4. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is guaranteed by design and characterization.
Data Sheet E0794E20 (Ver. 2.0)
14
EBE21RD4AGFA
Pin Capacitance (TA = 25C, VDD = 1.8V 0.1V)
Parameter Input capacitance Input capacitance Data and DQS input/output capacitance -6E -5C, -4A Symbol CI1 CI2 CO Pins Address, /RAS, /CAS, /WE, /CS, CKE, ODT CK, /CK DQ, DQS, /DQS, CB min. 2.5 2 2.5 2.5 max. 3.5 3 3.5 4.0 Unit pF pF pF pF Notes 1 2 3 3
Notes: 1. Register component specification. 2. PLL component specification. 3. DDR2 SDRAM component specification.
Data Sheet E0794E20 (Ver. 2.0)
15
EBE21RD4AGFA
AC Characteristics (TC = 0C to +85C , VDD, VDDQ = 1.8V 0.1V, VSS = 0V) (DDR2 SDRAM Component Specification)
-6E Frequency (Mbps) Parameter /CAS latency Active to read or write command delay Precharge command period Active to active/auto refresh command time DQ output access time from CK, /CK DQS output access time from CK, /CK CK high-level width CK low-level width CK half period Clock cycle time DQ and DM input hold time DQ and DM input setup time Control and Address input pulse width for each input DQ and DM input pulse width for each input Data-out high-impedance time from CK,/CK Data-out low-impedance time from CK,/CK DQS-DQ skew for DQS and associated DQ signals DQ hold skew factor Symbol CL tRCD tRP tRC tAC 667 min. 5 15 15 60 -450 max. 5 +450 +400 0.55 0.55 8000 tAC max. tAC max. 240 340 -5C 533 min. 4 15 15 60 -500 -450 0.45 0.45 min. (tCL, tCH) 3750 225 100 0.6 0.35 tAC min. tHP - tQHS max. 5 +500 +450 0.55 0.55 8000 tAC max. tAC max. 300 400 -4A 400 min. 3 15 15 55 -600 -500 0.45 0.45 min. (tCL, tCH) 5000 275 150 0.6 0.35 tAC min. tHP - tQHS max. 5 +600 +500 0.55 0.55 8000 tAC max. tAC max. 350 450 Unit tCK ns ns ns ps ps tCK tCK ps ps ps ps tCK tCK ps ps ps ps ps 5 4 Notes
tDQSCK -400 tCH tCL tHP tCK tDH tDS tIPW tDIPW tHZ tLZ tDQSQ tQHS 0.45 0.45 min. (tCL, tCH) 3000 175 100 0.6 0.35 tAC min. tHP - tQHS
DQ/DQS output hold time from tQH DQS Write command to first DQS tDQSS latching transition DQS input high pulse width DQS input low pulse width tDQSH tDQSL
WL - 0.25 WL + 0.25 WL - 0.25 WL + 0.25 WL - 0.25 WL + 0.25 tCK 0.35 0.35 0.2 0.2 2 0.4 0.35 275 200 0.9 0.4 0.6 1.1 0.6 0.35 0.35 0.2 0.2 2 0.4 0.35 375 250 0.9 0.4 0.6 1.1 0.6 0.35 0.35 0.2 0.2 2 0.4 0.35 475 350 0.9 0.4 0.6 1.1 0.6 tCK tCK tCK tCK tCK tCK tCK ps ps tCK tCK 5 4
DQS falling edge to CK setup tDSS time DQS falling edge hold time from tDSH CK Mode register set command tMRD cycle time Write postamble Write preamble tWPST tWPRE
Address and control input hold tIH time Address and control input setup tIS time Read preamble Read postamble tRPRE tRPST
Data Sheet E0794E20 (Ver. 2.0)
16
EBE21RD4AGFA
-6E Frequency (Mbps) Parameter Active to precharge command Symbol tRAS 667 min. 45 max. 70000 -5C 533 min. 45 max. 70000 -4A 400 min. 40 max. 70000 Unit ns ns ns ns tCK ns ns ns tCK tCK tCK tCK tCK ns ns s s ns 3 2, 3 1 Notes
Active to auto-precharge delay tRAP Active bank A to active bank B command period Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal read to precharge command delay Exit self refresh to a non-read command Exit self refresh to a read command Exit precharge power down to any non-read command Exit active power down to read command Exit active power down to read command (slow exit/low power mode) CKE minimum pulse width (high and low pulse width) Output impedance test driver delay Auto refresh to active/auto refresh command time Average periodic refresh interval (0C TC +85C) (+85C < TC +95C) Minimum time clocks remains ON after CKE asynchronously drops low tRRD tWR tDAL tWTR tRTP tXSNR tXSRD tXP tXARD
tRCD min. 7.5 15
tRCD min. 7.5 15
tRCD min. 7.5 15
(tWR/tCK)+ (tRP/tCK) 7.5 7.5
(tWR/tCK)+ (tRP/tCK) 7.5 7.5
(tWR/tCK)+ (tRP/tCK) 10 7.5
tRFC + 10 200 2 2 12 7.8 3.9
tRFC + 10 200 2 2 6 - AL 3 0 105 12 7.8 3.9
tRFC + 10 200 2 2 6 - AL 3 0 105 12 7.8 3.9
tXARDS 7- AL tCKE tOIT tRFC tREFI tREFI tDELAY 3 0 105
tIS + tCK + tIH
tIS + tCK + tIH
tIS + tCK + tIH
Notes: 1. 2. 3. 4.
For each of the terms above, if not already an integer, round to the next higher integer. AL: Additive Latency. MRS A12 bit defines which active power down exit timing to be applied. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test. 5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIH(DC) level for a rising signal and VIL(DC) for a falling signal applied to the device under test.
CK /CK
DQS /DQS
tIS
tIH
tIS
tIH VDDQ VIH (AC)(min.) VIH (DC)(min.) VREF VIL (DC)(max.) VIL (AC)(max.) VSS
tDS
tDH
tDS
tDH VDDQ VIH (AC)(min.) VIH (DC)(min.) VREF VIL (DC)(max.) VIL (AC)(max.) VSS
Input Waveform Timing 1 (tDS, tDH)
Input Waveform Timing 2 (tIS, tIH)
Data Sheet E0794E20 (Ver. 2.0)
17
EBE21RD4AGFA
ODT AC Electrical Characteristics (DDR2 SDRAM Component Specification)
Parameter ODT turn-on delay ODT turn-on -6E -5C, -4A ODT turn-on (power down mode) ODT turn-off delay ODT turn-off ODT turn-off (power down mode) ODT to power down entry latency ODT power down exit latency Symbol tAOND tAON tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD min 2 tAC(min) tAC(min) tAC(min) + 2000 2.5 tAC(min) tAC(min) + 2000 3 8 max 2 tAC(max) + 700 tAC(max) + 1000 2tCK + tAC(max) + 1000 2.5 tAC(max) + 600 2.5tCK + tAC(max) + 1000 3 8 Unit tCK ps ps ps tCK ps ps tCK tCK 2 1 1 Notes
Notes: 1. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND. 2. ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
AC Input Test Conditions
Parameter Input reference voltage Input signal maximum peak to peak swing Input signal maximum slew rate Symbol VREF VSWING(max.) SLEW Value 0.5 x VDDQ 1.0 1.0 Unit V V V/ns Notes 1 1 2, 3
Notes: 1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from VIL(DC) (max.) to VIH(AC) (min.) for rising edges and the range from VIH(DC) (min.) to VIL(AC) (max.) for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative transitions.
Start of falling edge input timing Start of rising edge input timing
VDDQ VIH (AC)(min.) VIH (DC)(min.)
VSWING(max.)
VREF VIL (DC)(max.) VIL (AC)(max.) TF TR Rising slew = VSS VIH (AC) min. - VIL (DC)(max.) TR
Falling slew =
VIH (DC)(min.) - VIL (AC)(max.) TF
AC Input Test Signal Wave forms
Measurement point DQ RT =25 VTT
Output Load
Data Sheet E0794E20 (Ver. 2.0)
18
EBE21RD4AGFA
Pin Functions
CK, /CK (input pin) The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross point of the CK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross point of the CK and the /CK. When a write operation, DQs are referred to the cross point of the DQS and the VREF level. DQSs for write operation are referred to the cross point of the CK and the /CK. /CS (input pin) When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. /RAS, /CAS, and /WE (input pins) These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. See "Command operation". A0 to A13 (input pins) Row address (AX0 to AX13) is determined by the A0 to the A13 level at the cross point of the CK rising edge and the VREF level in a bank active command cycle. Column address (AY0 to AY9, AY11) is loaded via the A0 to the A9 and A11 at the cross point of the CK rising edge and the VREF level in a read or a write command cycle. This column address becomes the starting address of a burst operation. A10 (AP) (input pin) A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = high when read or write command, auto-precharge function is enabled. While A10 = low, auto-precharge function is disabled. BA0, BA1 (input pin) BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See Bank Select Signal Table) [Bank Select Signal Table]
BA0 Bank 0 Bank 1 Bank 2 Bank 3 L H L H BA1 L L H H
Remark: H: VIH. L: VIL. CKE (input pin) CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the CKE is driven low and exited when it resumes to high. The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge and the VREF level with proper setup time tIS, at the next CK rising edge CKE level must be kept with proper hold time tIH. DQ, CB (input and output pins) Data are input to and output from these pins. DQS (input and output pin) DQS and /DQS provide the read data strobes (as output) and the write data strobes (as input).
Data Sheet E0794E20 (Ver. 2.0)
19
EBE21RD4AGFA
VDD (power supply pins) 1.8V is applied. (VDD is for the internal circuit.) VDDSPD (power supply pin) 1.8V is applied (For serial EEPROM). VSS (power supply pin) Ground is connected. /RESET (input pin) LVCMOS reset input. When /RESET is Low, all registers are reset. Par_IN (Parity input pin) Parity bit for the address and control bus. Err_Out (Error output pin) Parity error found on the address and control bus.
Detailed Operation Part and Timing Waveforms
Refer to the EDE5104AGSE, EDE5108AGSE datasheet (E0715E). DM pins of component device fixed to VSS level on the module board. DIMM /CAS latency = component CL + 1 for registered type.
Data Sheet E0794E20 (Ver. 2.0)
20
EBE21RD4AGFA
Physical Outline
Unit: mm
4.00 max (DATUM -A-)
0.5 min
Component area (Front)
1 120
B 63.00 133.35 55.00
A 1.27 0.10
240
10.00
121
17.80
4.00 min
Component area (Back)
4.00
FULL R
3.00
Detail A
2.50 0.20
Detail B 1.00 4.00
0.20 0.15
(DATUM -A-)
2.50 FULL R
5.00
3.80
0.80 0.05
1.50 0.10
ECA-TS2-0093-01
Data Sheet E0794E20 (Ver. 2.0)
21
30.00
EBE21RD4AGFA
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. In particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. When re-packing memory modules, be sure the modules are not touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
MDE0202
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
CME0107
Data Sheet E0794E20 (Ver. 2.0)
22
EBE21RD4AGFA
BGA is a registered trademark of Tessera, Inc. All other trademarks are the intellectual property of their respective owners.
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
M01E0107
Data Sheet E0794E20 (Ver. 2.0)
23

▲Up To Search▲

Price & Availability of EBE21RD4AGFA-6E-E

	To Download EBE21RD4AGFA-6E-E Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .